1. Field of the Invention
The present invention relates to an oscillator circuit.
2. Description of Related Art
Heretofore, an oscillator circuit for realizing lower power consumption has been provided with a configuration as shown in FIG. 1. This circuit is described specifically by referring to this figure. A CMOS inverter 101 is connected with a higher-potential power supply 103 and with a lower-potential power supply 104 via current-limiting devices 102 that are used to realize lower power consumption. One electrode of a load capacitor 105 is connected with the input side of the CMOS inverter 101, while the other electrode is connected with the lower-potential power supply 104. One electrode of a load capacitor 106 is connected with the output side of the CMOS inverter 101, whereas the other electrode is connected with the lower-potential power supply 104. Also shown are a quartz oscillator 107 and a feedback resistor 108.
In the above-described configuration, however, the load capacitors 105 and 106 directly connected with the power supplies cause the circuit to have the problem that the power-supply voltages vary greatly in synchronism with the oscillation. Therefore, any circuit using a power supply in common with this oscillator circuit has the disadvantage of becoming unstable in operation. Conversely, where the power-supply voltages are varied by some action independent of the oscillation, there is also the disadvantage that the variations adversely affect the oscillator circuit.
Where an oscillator circuit IC including a CMOS inverter having an externally attached quartz oscillator is connected with a buffer circuit IC, it is common practice to attach an AC coupling capacitor externally to an output of the CMOS inverter within the oscillator circuit and to connect the input terminal of the buffer circuit via the coupling capacitor.
A protective circuit is mounted to the input terminal portion of the buffer circuit. This protective circuit has an electrostatic capacity of about 5 pF. Accordingly, the electrostatic capacity of the AC coupling capacitor is required to be large enough to be capable of canceling out the electrostatic capacity of the protective circuit, e.g., approximately 100 pF. This increases the size of the AC coupling capacitor that must be attached externally. In consequence, the circuit scale is increased.
In the present invention, the first load capacitor is connected between the input side of a CMOS inverter and one power-supply potential, the second load capacitor is connected between the input side of the CMOS inverter and the other power-supply potential, the third load capacitor is connected between the output side of the CMOS inverter and the one power-supply potential, and the fourth load capacitor is connected between the output side of the CMOS inverter and the other power-supply potential. Thus, variations in the power-supply voltages in synchronism with oscillation can be reduced with the realization of lower electric current consumption.
Since the first and third load capacitors and one power-supply side of the CMOS inverter are coupled to the one power-supply voltage via the first current-limiting device, and the second and fourth load capacitors and the other power-supply side of the CMOS inverter are coupled to the other power-supply voltage via the second current-limiting device, variations in the power-supply voltages in synchronism with oscillation can be reduced further with the realization of lower current consumption.
The first and second current-limiting devices may be resistors.
The first and second current-limiting devices may be transistors.
The first and second current-limiting devices may be constant current circuits.
Each of the first and second current-limiting devices is made of a plurality of switching devices connected in parallel. These switching devices are controlled by a control circuit according to the output from the CMOS inverter. This therefore enables the current-limiting devices to be adjusted, so that optimum adjustment becomes possible. Moreover, for example, by controlling the switching devices so that a large amount of current flows via these switching devices at the start of oscillation and so that a desired amount of current flows after the oscillation has been stabilized, the time between the start of the oscillation and the stabilization of the oscillation can be shortened to enhance the responsiveness.
Further in accordance with the present invention, a CMOS inverter for oscillations, an AC coupling capacitor, and a buffer circuit are formed on one chip, thus dispensing with a protective circuit that would normally be mounted at the input terminal portion of the buffer circuit. Consequently, the electrostatic capacity of the AC coupling capacitor can be reduced and thus the circuit scale can be decreased.
Advantages similar to the foregoing can be obtained by forming the AC coupling capacitor and the buffer circuit on one chip.
An invention as set forth in one aspect lies in an oscillator circuit comprising a CMOS inverter producing an output and a buffer circuit for receiving the output from the inverter via an AC coupling capacitor. A quartz oscillator is connected across input and output of the CMOS inverter. The AC coupling capacitor, the CMOS inverter, and the buffer circuit are formed on one chip.
An invention as set forth in another aspect lies in an oscillator circuit comprising a CMOS inverter producing an output and a buffer circuit for receiving the output from the inverter via an AC coupling capacitor. A quartz oscillator is connected across input and output of the CMOS inverter. The AC coupling capacitor and the buffer circuit are formed on one chip.